Method for producing a non-volatile memory cell using spacers

ABSTRACT

Method for producing a non-volatile memory cell and obtained memory cell. This method consists of embodying strips in a stacking of one nonconducting film and one conductive film, both films intended to respectively form the gate nonconductors (210) and the floating gates (208) of transistors, of forming spacers (230) on the flanks of the strips of said stacking, of eliminating the spacers on the side of the drains of the memory points to be embodied, of implanting ions of a type with conductivity differing from that of the substrate by using the remaining spacers and the strips of said stacking as a mask so as to form the sources and drains (214, 216) of the transistors, respectively offset and aligned with respect to said strips, of eliminating the remaining spacers, of forming a thin electric nonconducting film (208) on the sources and drains of the transistors, of embodying conductive strips (206a) perpendicular to the diffused source and drain zones, and of etching the strips of said stacking by using the conductive strips as a mask.

FIELD OF THE INVENTION

The present invention concerns a method for producing an integratednon-volatile memory cell with a floating gate, as well as the cell thusobtained. More specifically, the invention concerns the production ofEPROM (erasable programmable read-only memory) and EEPROM (electricallyerasable programmable read-only memory) memory cells, these memoriespossibly being of the flash type.

BACKGROUND OF THE INVENTION

In particular, the invention is applicable for the production of MOS orCMOS type integrated memory circuits.

An integrated EEPROM or EPROM memory is an integrated circuit includingone actual memory portion known as a memory cell formed from a matrix ofseveral electrically interconnected memory points and peripheralcircuits used to control the memory points.

The invention solely deals with the actual memory portion.

The invention is adapted to any generation of drawing rules. It isneverthesless applicable to the embodiment of non-volatile memories witha high integration density allowing at least for the storage of 10binary elements (≧1 Mbits). In fact, this method makes it possible toreduce the surface of the memory point and thus mainly concerns memorycells with micronic or submicronic drawing rules and typically withfloating gate widths of 0.6 μm.

FIGS. 1 and 2 diagrammatically show one known type of EPROM memory cellembodied and drawn according to the conventional cells concept or with aT shape ; FIG. 1 is a top view and FIG. 2 is a longitudinal sectionalong the direction II--II of FIG. 1.

For the purpose of simplification, this cell comprises per memory point2 one floating gate 4 and one polycrystalline silicon control gate 6stacked and isolated from each other by an intergate nonconductor 8, onegate nonconductor 10 inserted between the silicon substrate 12 and thefloating gate 4, one source zone 14 diffused in the substrate 12, onedrain zone 16 diffused in the substrate and one metallic electrichalf-contact 18. The reference D denotes all the diffused zones. Eachdrain zone 16 is common to two consecutive memory points.

Each memory point is the result of the crossing of a line of words 6aformed as the gate 6 in the upper polycrystalline silicon film and theline 18a of binary elements, hereinafter referred to as bits, embodiedin the same film as the electric half-contact.

This type of memory point has been used for a large number of years fromthe generations of several kilobits up to the currently most advancedcircuits of between 4 and 16 Mbits.

It main advantage resides in the wide experience acquired by EPROMmemory manufacturers concerning this type of memory point and theforeseeable continuity when a memory generation advances to the nextone.

However, with the increase in density integration, it is becomingincreasingly difficult to make this memory evolve to having smallerdimensions as misalignments from level to level represent a considerableportion of its surface. For example, the memories of 1 Mbits embodiedwith conventional T memory points currently have a surface of about 45mm2 for a memory point surface of between 18 and 20 μm2, and memories of4 Mbits have a surface of between about 70 and 80 mm2 for a memory pointsurface of between 9 and 10 μm2.

Moreover, the traditional memory cell comprises one half-contact permemory point and for densities of several megabits, several millions ofcontacts are embodied in the circuit ; this then poses the problem ofthe density of defects concerning this type of metallization requiringsignificant control of the latter and possibly resulting in circuitsmalfunctioning on account of incorrect electric connection.

Several years ago, Boaz Eitan of the Wafer Scale Integration companyproposed a new type of EPROM memory point known as a "Self-aligned Splitgate EPROM". This memory point with a "split" gate is described indetail in the document U.S. Pat. No. 4,639,893 of Jan. 27, 1987.

FIGS. 3 and 4 diagrammatically show a known type of a "split gate" EPROMmemory cell ; FIG. 3 is a top view and FIG. 4 is a longitudinal cutawayview along the line IV--IV of FIG. 3.

These figures show for each memory point 102 the floating gate 104 andthe control gate 106 isolated by the intergate nonconductor 108, thegate nonconductor 110, and the source 114 and drain 116 zones diffusedin the substrate 112. The gates 104 and 106 are made of polycrystallinesilicon. The control gates 106 are constituted by the portion of thelines of words 106a opposite the floating gates 104.

This memory point 102 has the advantage of being formed via the crossingof lower polycrystalline silicon blocks 104 and lines of upperpolycrystalline silicon lines of words 106a. In addition, this memorypoint has the advantage of not comprising any electric contact ; thecontact of the bit lines (that is on the drain lines) is solely taken upevery 16 or even 32 memory points.

This "split gate" memory point thus allows, with drawing rules identicalto those of the T-shaped cells, a smaller surface of memory points to beobtained whilst considerably reducing the electric contact number in thememory plane. Thus, using this concept, the WSI company recentlyannounced the embodiment of an EPROM memory of 1 Mbits, a surface of 26mm2 with memory points of 9.5 μm, then a memory of 4 Mbits, a surface of65 mm2 embodied with the same memory point dimensions.

To this effect, reference may be made to the article in VLSI Symposiumon Circuits, Kyoto, 1989 by S. All and al and entitled "A new staggeredVirtual Ground array architecture Implemented in a 4Mb CMOS EPROM", pp.35-36.

Moreover, the conception of the "split gate" memory point includes theembodiment of an access transistor connected in series with the doublepolycrystalline silicon gate.

In the rest of the description, the lower film of polycrystallinesilicon shall be denoted as poly-1 and the upper polycrystalline siliconfilm as poly-2.

This access transistor is embodied by the separation zone 120 betweenthe source zone 114, generally of the type N+, and the floating gate104. This separation zone, controlled by the poly-2 gate of the line ofwords, modulates the effective electric length of the channel of thememory point according to the voltage applied to the poly-2.

When the voltage of the poly-2 gate (or line of words) is nil, thischannel zone controlled by the poly-2 is blocked and the memory pointdoes not operate. This makes it possible to considerably reduce thestray current of the memory points of a given progamming addressed lineof bits but not situated on the same line of words ; this stray currentis induced via the coupling of the drain with the floating gate (turn-onphenomenon).

This access transistor also makes it possible to envisage electricwidths under the floating gate much smaller than those of the T memorypoints without running the risk of piercing between the source and drainof the memory points. Finally, it makes it possible to reduce thethreshold voltage of the nonprogrammed memory points and thus increasetheir reading current.

However, this zone for separating the source and floating gatecontrolled by the line of words is embodied in the patent of Boaz Eitanby positioning a resin mask on the poly-1. If this masking is notcritical for floating gate widths of about one micrometer, it becomesmore difficult for submicronic floating gate widths (such as 0.6 μm forthe generation of a 16 Mbit memory).

The misalignment of this mask with respect to the floating gates has infact a direct effect on the width of the source of each seriestransistor and on the electric length (or channel) of the series MOStransistor.

All the drawbacks mentioned above also exist in flash or non-flash typeEEPROM memories which merely constitute special EPROMS.

SUMMARY OF THE INVENTION

Accordingly, the object of the invention is to provide a method forembodying a non-volatile memory cell of the type without any electriccontact in each memory point and with access transistors connected inseries with the double gates making it possible to resolve theabove-mentioned drawbacks. In particular, this method ensures anautomatic alignment of the series transistor with respect to thefloating gate of the associated memory point, thus making it possible tohave a constant channel length of this transistor, as well as a fixedsource length of said transistor.

The principle of the invention consists of using, for offsetting betweenthe source and the floating gate of each memory point, a spacer embodiedon the flanks of each floating gate, said spacer having the advantage ofhaving a fixed size and being self-aligned with respect to the floatinggate.

More specifically, the invention concerns a method for producing anon-volatile memory cell on a semiconductive substrate with a given typeof conductivity and comprising :

a) - a matrix of memory points electrically isolated from one anotherand each provided with a stacking of one floating gate and one controlgate both electrically isolated from each other, a gate nonconductorinserted between the floating gate and the substrate, one source and onedrain formed in the substrate on both sides of the stacking, one channelsituated under the floating gate having a length orientated along adirection extending from the source to the drain, and one accesstransistor connected in series to the stacking of the gates,

b) - lines of words constituted by conductive strips parallel to thisdirection, this method including the following stages :

1) - embodying on the substrate a stacking of one electric nonconductingfilm and one conductive film intended to respectively form the gatenonconductors and the floating gates,

2) - etching of this stacking of films so as to form the strips of saidstacking perpendicular to said direction,

3) - embodying of spacing strips on the flanks of the strips of saidstacking and made of a material able to be selectively etched withrespect to the conductive film of the stacking and to the substrate,

4) - elimination of the spacing strips on the side of the drains to beembodied,

5) - implantation of ions with conductivity differing from that of thesubstrate by using the remaining spacing strips and the strips of saidstacking as a mask so as to form the sources and drains of thetransistors respectively offset and aligned with respect to the stripsof said stacking,

6) - elimination of the remaining spacing strips,

7) - forming of a thin electric nonconducting film on the sources anddrains of the transistors and on the strips of said stacking,

8) - embodying of conductive strips on the strips of said stacking,these conductive strips being parallel to said direction and thusforming the control gates and the lines of words, and

9) - etching of the strips of said stacking by using said conductivestrips as a mask so as to fix the dimensions of the floating gates andthe gate nonconductors.

In other words, the lines of words and the control gates are merged inthe same strips.

The memory cell obtained has the particular feature of not having anyelectric contact in the specific memory point and of having an accesstransistor connected in series with the stacking of gates ; thistransistor is self-aligned with respect to the floating gate of eachmemory point and its dimensions are fixed.

By using a width and length of the floating gate both of 0.6 μm, it isposisble to attain with the method of the invention a memory pointsurface of 1.96 μm2, whereas currently the smallest memory pointdimensions published with these drawing rules for T cells are aboutbetween 3.5 and 4μm, which corresponds to a gain close to 2 in terms ofintegration density.

According to the invention, it is possible to use control gates andlines of words made of metal (Al, W, Ta, Mo), a silicide of a refractorymetal (TiSi₂, TaSi ₂, WSi₂, PtSi) or made of polycrystalline silicondoped with phosphorus (0.5 to 2% in weight).

When the floating gates are made of polycrystalline silicon doped withphosphorus and the substrate is made of monocrystalline silicon, thethin electric nonconducting film formed during stage 7 is advantageouslyobtained by the thermic oxidation of the polycrystalline andmonocrystalline silicon. In this case, the thermic oxidation of thepolycrystalline silicon intended to produce the floating gates makes itpossible to embody the inter-gate nonconductors.

It is possible to replace this thermic oxidation stage by depositing oneor several electric nonconductors, such as silicon oxinitride, siliconnitride or silicon oxide.

When it is desired to embody the inter-gate nonconductors by means otherthan by the thermic oxidation of the polycrystalline silicon of thefloating gates, it is preferable to protect these inter-gatenonconductors throughout all the subsequent stages of the productionmethod.

Also, in one preferred embodiment, the method of the invention forproducing a memory cell comprises the following stages :

i) - embodying on the substrate a stacking of one first electricnonconducting film intended to form the gate nonconductors, one firstconductive film intended to form the floating gates, at least one secondfilm of an electric nonconductor intended to form the intergatenonconductors, one second conductive film intended to embody the controlgates and one protection film able to be selectively etched with respectto the second conductive film,

ii) - etching of this stacking of films so as to form the strips of saidstacking perpendicular to said direction,

iii) - embodying spacing strips on the flanks of the strips of saidstacking, these strips being made of a material able to be etchedselectively with respect to the protection film and to the substrate,

iv) - elimination of the spacing strips on the side of the drains to beembodied,

v) - implantation of ions with conductivity differing from that of thesubstrate by using the remaining spacing strips and the strips of saidstacking of films as a mask so as to form the sources and drains of thetransistors respectively offset and aligned with respect to the stripsof said stacking,

vi) - elimination of the remaining spacing strips,

vii) - forming a thin electric nonconducting film on the sources anddrains of the transistors,

viii) elimination of the protection film,

ix) embodying conductive strips on the strips of said stacking obtainedat viii), these conductive strips being parallel to said direction andthus forming the lines of words, and

x) - etching of the strips of said stacking obtained at viii) by usingsaid conductive strips as a mask so as to fix the dimensions of thecontrol gates, the inter-gate nonconductors, the floating gates and thegate nonconductors.

Here, the lines of words and the control gates are distinct and made,for example, of two different conductive materials.

In this embodiment, the inter-gate nonconductors (that is the secondnonconducting film) may be made with any type of nonconducting materialand in particular via a trifilm stacking of silicon oxide, siliconnitride and silicon oxide, generally called ONO.

Moreover, in this embodiment, the second conductive film may be made ofone of the silicides mentioned above or of polycrystalline silicon dopedwith between 0.5 and 2% in weight of phosphorus.

So as to use this conductive film so as to ensure the electric contactwith the line of words of each memory point, it is necessary to protectthis second conductive film against thermic oxidation by means ofproviding a protection film (see stage i). This protective film may bemade of silicon nitride, for example.

The protection film also allows for etching of the spacing stripsfollowed by a reoxidation of the surface and drain zones withoutmodifying the structure of the inter-gate nonconductor and in particularthe ONO stacking.

The spacing strips may be made of any electric nonconducting material,such as silicon nitride, silicon oxynitride or silicon oxide or even ofnondoped polycrystalline silicon, the only restriction of these spacingstrips being their aptitude for being selectively etched with respect tothe subjacent materials (in particular with respect to the materialintended for the floating gates of the memory points, the protectionfilm and the substrate).

Similarly, the gate nonconductors may be made of silicon oxide orsilicon oxynitride for example.

So as to reduce the access resistance of the lines of words, when theselines of words are made of doped polycrystalline silicon, it is possibleto coat them with a silicide film of a refractory metal as referred toearlier.

BRIEF DESCRIPTION OF THE DRAWINGS

Other characteristics and advantages of the invention shall appear morereadily from a reading of the following description, given by way ofnonrestrictive illustration, with reference to the accompanying drawingson which

FIGS. 1 and 2, already described, diagrammatically show one EPROMT-shaped memory cell according to the prior art ;

FIGS. 3 and 4, already described, diagrammatically show a known type of"split gate" memory cell ;

FIGS. 5 to 12 diagrammatically show the various stages of the method ofthe invention, FIGS. 5 to 11 being longitudinal sections and FIG. 12 atop view, and

FIGS. 13 to 15 diagrammatically show a longitudinal section of onevariant of the method of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following description refers to the production of an EPROM memorycell so as to simplify this description. However, as seen earlier, theinvention can be applied more generally as it is applicable to all typesof non-volatile memory cells.

The method shown below is described after the embodiment of the caissonsN and P, field isolation, doping under the field nonconductor so as toisolate the active zones, sacrificial oxidation, as well as doping ofthe semiconductive substrate of the memory points so as to adjust thethreshold voltage of these memory points. These elements are embodied asin the prior art.

Finally, the following description refers to a type P siliconmonocrystalline substrate, this substrate bearing the reference 212.

As shown on FIG. 5, a thermic oxidation 210 is effected inside thememory plane of the silicon 212 over a thickness of 20 nm, for example,at a temperature of 1000° C. under dry oxygen. This thermic oxidationshall be used to embody the gate nonconductors.

Then a deposit is effected of the lower polycrystalline silicon 204(poly-1) with a thickness of 150 nm by means of low pressure chemicalvapor depositing. This deposit 204 shall be used for embodying thefloating gate of the memory points.

This polycrystalline silicon 204 is then doped via the diffusion ofphosphorus (0.5 to 2% in weight) in an oven at 950° C.

Then a nonconducting material 208 is deposited in which the inter-gatenonconductors are to be embodied. This deposit successively consists ofone thermic oxidation of the polycrystalline silicon 204, one lowpressure chemical vapor depositing of a fine nitride film (mixture ofNH₃ and SiH₂ Cl₂ ) at 800° C. and then a slight thermic reoxidation ofthis nitride so as to obtain an equivalent thickness in SiO₂ of thistrifilm of 20 nm.

Then a 150 nm film of polycrystalline silicon 222 is deposited via lowpressure chemical depositing at 620° C. The doping of this silicon (0.5to 2% in weight) is also carried out via the diffusion of phosphorus inan oven at 950° C.

Finally, a fine film of silicon nitride 224 is deposited on thispolycrystalline silicon film 222 by means of low pressure chemical vapordeposit at 800° C., this film 224 having a thickness of 50 nm. This filmshall be used to avoid any reoxidation of the subjacent silicon film 222during the source and drain reoxidation and thus shall allow for a goodcontact between this polycrystalline silicon and the bi-film(silicide+poly-2) of the lines of words.

After stacking of all these films, the first level of silicon (poly-1)is masked by means of slice direct photorepetition photolithographywell-known to experts in this field. This mask fixes the dimension ofthe floating gates according to the direction x of the channels andmasks the poly-1 zones to be preserved. It appears in the form of stripsperpendicular to the direction x.

The etching of the stacking of the films 204, 208, 222 and 224 is theneffected by dry etching, for example by reactive ionic etching by usingsulfur hexafluoride SF₆ and thus coming to a stop inside the gate oxide210. The masking resin 226 is then eliminated under vacuum via an oxygenplasma. The structure obtained is shown on FIG. 6.

Strips 227 of the stacking of the films 204, 208, 222 and 224 areobtained perpendicular to the direction x whose width is equal to thelength of the floating gates to be embodied.

Next, the spacing strips or spacers are embodied. These spacers may bemade of silicon oxide, silicon nitride or polycrystalline silicon. Therenow follows a description of one embodiment using silicon oxide spacers.

After the low pressure chemical vapor depositing at 800° C. of a siliconoxide film 228 from tetraethoxysilane (TEOS) and with a thickness of 400nm (FIG. 6), an anisotropic etching is made of this oxide via plasmaetching, gas CHF₃, so as to embody, as shown on FIG. 7, oxide spacers230 with a width of 200 nm on the flanks of the strips 227 (over theentire length of the strips).

The elimination of the spacers on the side of the drains of the memorypoints to be embodied is then effected with the aid of aphotolithographic mask 232 aligned on the stacking of the films and inparticular on the poly-1 204, followed by a chemical etching with asolution of FH-FNH₄. The structure obtained is shown on FIG. 8. (Themask 232 comprises openings 234 opposite the substrate regions intendedfor the drains and one portion of each poly-1 strip 204).

After elimination of this resin mask by an oxygen plasma, the ionicimplantation N+is made of the memory points with arsenic at an energy of70 KeV and a dose of 3×10⁵ at.cm2.

The structure obtained is the one shown on FIG. 9.

By means of the implantation of ions N+by using the etched film strips227 and the remaining spacers 230 as an implantation mask, strips areobtained diffused in the substrate 212, said strips belong parallel toone another and perpendicular to the direction x of the channel of thememory points. The diffused zones are situated offset on the source side214 by a constant distance 1 from each strip 227, whereas they areautomatically aligned with respect to these strips 227 on the side ofthe drain 216 of the memory points.

Thus, the drains are self-aligned with respect to the floating gates andan offsetting 1 of the sources is obtained with respect to these gates.

Then the remaining spacers 230 on the source side are eliminated via achemical etching by using a solution of FH-FNH₄.

Then this ionic implantation is annealed, for example, at 850° C. for 30minutes so as to make the implanted ions diffuse and electricallyactivate them. The structure obtained is the one shown on FIG. 10.

Then the source and drain zones are reoxidized 236 via thermic oxidationof the silicon 212 over a thickness of 20 nm at 1000° C. under dryoxygen.

During this reoxidation, the nitride film 224 of each memory pointprevents any thermic oxidation of the sub-jacent polycrystalline siliconfilm 222. Next, this silicon nitride film is eliminated by chemicaletching with the aid of an orthophosphoric bath at 150° C. The structureobtained is shown on FIG. 11.

Then the upper polycrystalline silicon film 206 constituting the levelof poly-2 is deposited by low pressure chemical vapor depositing at 620°C. and has a thickness of 250 nm. This silicon film 206 is then dopedvia the diffusion of phosphorus in an oven at 950° C. and with aconcentration of between 0.5 and 2% in weight. Finally, a film oftungsten silicide 238 is advantageously deposited via low pressurechemical vapor depositing at 400° C. and has a thickness of 200 nm.

The poly-2 film 206 is in contact with the etched silicon film 222 andthus ensures electric contact with the lines of words.

The method of the invention is then continued by masking the structureby a mask constituted by strips parallel to the direction x and then bythe etching of the films 206 and 238 in the form of strips 206a, asshown on FIG. 12, constituting the lines of words. These strips 206a areperpendicular to the diffused strips 214 and 216 and are thus parallelto the direction x.

Then the strips 227 coming to a stop on the substrate are etched byusing the mask for etching the lines of words 206a as a mask so as toobtain the final dimensions of the floating gates, the inter-gatenonconductors, the gate nonconductors and the control gates constitutedhere by the conductive blocks 222. The etching mask is then eliminated.

In accordance with the prior art, the peripheral transistors N and P ofthe memory are embodied, followed by depositing and then the creep orflow of one electric conductor film on the entire integrated circuit,the opening of contact holes in this nonconductor opposite the diffusedzones 214 and 216 in particular, the metallization of the lines of bitsand finally the passivation of the entire circuit with the aid of anelectric nonconductor.

With the method of the invention, by using 0.6 μm drawing rules, it ispossible to embody memory points 202 with a surface smaller than 2 μm2,whereas the smallest memory points curently published are between about3.5 and 4 μm2.

It is thus possible to embody memory points with a surface of between1.96 and 2.5 μm2, a floating gate width L' and a length L ofrespectively 0.6 μm : a distance D separating two lines of words 206a of0.8 μm; a width L' of the lines of words 206a of 0.6 μm ; and a distanced separating two floating gates of 0.8 μm.

With drawing rules of 0.4 μm (L=L'=0.4 μm), it is possible to obtainmemory points with a surface of 1.5 μm2.

Thus, the distance 1 (fixed by the width of the spacers) is 0.2 μm whichcorresponds to the offsetting between the source and the stacking of thegates of one memory point. This separation zone defines the MOS accesstransistor connected in series with the gates. It bears the reference120 on FIG. 11. The length of its channel is equal to 1.

FIGS. 13 to 15 show one variant of the method of the invention. In thisvariant, the inter-gate nonconductor is embodied during reoxidation ofthe sources and drains of the memory points. Thus, it is no longernecessary to use the polycrystalline silicon film 222 or the nitridefilm 224.

Also, as shown on FIG. 13, after the depositing of the gatenonconducting film 210 and then the poly-1 silicon film 204, thisstacking is etched so as to fix the length of the floating gate. Then asilicon oxide film 400 nm thick, intended to to form the spacers, isdeposited on the entire structure, followed by an etching of this filmso as to form the spacers 230.

After formation of the lithographic mask 232 allowing for theself-alignment of the drains with respect to the floating gate 204 andthe offsetting of the sources, the spacers on the drain side areeliminated and then the resin mask 232 used for this elimination is alsoeliminated. The structure obtained is shown on FIG. 14.

After the implantation N+, as described earlier, the remaining spacerson the source side are eliminated and then the sources and drains of thememory points are reoxidized and the floating gates 204 are oxidized.Thus, an inter-gate nonconductor 208a made of silicon oxide 20 nm thickis obtained.

The method is continued, as shown on FIG. 15, via the depositing of thepolycrystalline silicon film (poly-2) 206 and the silicide film 238. Therest of the method remains unchanged.

What is claimed is:
 1. Method for producing a non-volatile memory cellon a semiconductive substrate with a given type of conductivity andcomprising :a) - a matrix of memory points electrically isolated fromone another and each provided with a stacking of one floating gate andone control gate, both gates electrically isolated from each other, onegate nonconductor inserted between the floating gate and the substrate,one source and one drain both formed in the substrate on both sides ofthe stacking, one channel situated under the floating gate and having alength orientated along a direction extending from the source to thedrain, and one access transistor connected in series to the stacking ofgates, b) - lines of words constituted by conductive strips parallel tothis direction, this method including the following stages : 1) -embodying on the substrate a stacking of one electric nonconductive filmand one conductive film respectively intended to form the gatenonconductors and the floating gates, 2) - etching of this stacking offilms so as to form the strips of said stacking, said strips beingperpendicular to said direction, 3) - embodying of spacing strips on theflanks of the strips of said stacking made of a nonconducting materialable to be selectively etched with respect to the conductive film of thestacking and to the substrate, 4) - elimination of the spacing strips onthe side of the drains to be embodied, 5) - implantation of ions with atype of conductivity differing from that of the substrate by using theremaining spacing strips and the strips of said stacking as a mask so asto form the sources and drains of the transistors, respectively offsetand aligned with respect to the strips of said stacking, 6) eliminationof the remaining spacing strips, 7) formation of a thin electricnonconductive film on the sources and drains of the transistors and onthe strips of said stacking, 8) - embodying of conductive strips on thestrips of said stacking, these conductive strips being parallel to saiddirection and thus forming the control gates and the lines of words, and9) - etching of the strips of said stacking by using said conductivestrips as a mask so as to fix the dimensions of the floating gates andthe gate nonconductors.
 2. Method according to claim 1, wherein thesubstrate and the floating gates are made of silicon and wherein thethin nonconducting film is obtained by oxidizing the silicon.
 3. Methodfor producing a non-volatile memory cell on a semiconductive substratewith a given type of conductivity and comprising :a) - a matrix ofmemory points electrically isolated from one another and each providedwith a stacking of one floating gate and one control gate, both gateselectrically isolated from each other, one gate nonconductor insertedbetween the floating gate and the substrate, one source and one drain,both formed in the substrate on both sides of the stacking, one channelsituated under the floating gate and having a length orientated along adirection extending from the source to the drain, and one accesstransistor connected in series to the stacking of gates, b) - lines ofwords constituted by conductive strips parallel to this direction, thismethod including the following stages : i) - embodying on the substratea stacking of one first electric nonconducting film intended to form thegate nonconductors, one first conductive film intended to form thefloating gates, at least one second electric nonconducting film intendedto form the intergate nonconductors, one second conductive film intendedto embody the control gates and one protection film able to beselectively etched with respect to the second conductive film, ii) -etching of this stacking of films so as to form the strips of saidstacking, said strips being perpendicular to said direction, iii) -embodying of spacing strips on the flanks of the strips of saidstacking, these strips being made of a nonconductive material able to beselectively etched with respect to the protection film and to thesubstrate, iv) - elimination of the spacing strips on the side of thedrains to be embodied, v) - implantation of ions with a type ofconductivity differing from that of the substrate by using the remainingspacing strips and the strips of the stacking of films as a mask so asto form the sources and drains of the transistors respectively displacedand aligned with respect to the strips of said stacking, vi) -elimination of the remaining spacing strips, vii) - formation of a thinelectric nonconducting film on the sources and drains of thetransistors, viii) - elimination of the protection film, ix) - embodyingof conductive strips on the strips of said stacking obtained at viii),these conductive strips being parallel to said direction and thusforming the lines of words, and x) - etching of the strips of saidstacking obtained at viii) by using said conductive strips as a mask soas to fix the dimensions of the control gates, the inter-gatenonconductors, the floating gates and of the gate nonconductors. 4.Method according to claim 3, wherein the intergate nonconductor is madeof a silicon oxide, silicon nitride and silicon oxide trifilm material.5. Method according to claim 3 or 4, wherein the second conductive filmis composed of doped polycrystalline silicon.
 6. Method according toclaim 5, wherein the protection film is composed on silicon nitride. 7.Method according to claim 1, wherein the conductive strips are made of abifilm material.
 8. Method according to claim 1, wherein an annealing iscarried out after the implantation of ions so as to make these ionsdiffuse inside the substrate and activate them.
 9. Method according toclaim 3, wherein the conductive strips are made of a bifilm material.10. Method according to claim 3, wherein an annealing is carried outafter the implantation of ions so as to make these ions diffuse insidethe substrate and activate them.